Low-k dielectric layer based upon carbon nanostructures

ABSTRACT

A low-k dielectric material for use in the manufacture of semiconductor devices, semiconductor structures using the low-k dielectric material, and methods of forming such dielectric materials and fabricating such structures. The low-k dielectric material comprises carbon nanostructures, like carbon nanotubes or carbon buckyballs, that are characterized by an insulating electronic state. The carbon nanostructures may be converted to the insulating electronic state either before or after a layer containing the carbon nanostructures is formed on a substrate. One approach for converting the carbon nanostructures to the insulating electronic state is fluorination.

FIELD OF THE INVENTION

The invention relates generally to semiconductor materials, structures,devices, and fabrication methods and, more particularly, to dielectricmaterials for forming a structure for an integrated circuit, structuresformed with the dielectric materials, and methods for forming suchdielectric materials and structures.

BACKGROUND OF THE INVENTION

Progressive miniaturization of feature sizes in circuit elements hasimproved the performance and increased the functional capability ofintegrated circuits (IC's). Back-end-of-line (BEOL) multilevelinterconnect structures have been developed that complement advances incircuit element density realized by size reductions by more effectivelyrouting signal paths between the constituent circuit elements of the IC.Circuit performance and functional capability of the circuit elementsare eventually limited by the signal-transmission effectiveness andefficiency of the BEOL interconnect structure. Damascene processes areroutinely used to fabricate such BEOL multilevel interconnectstructures. In a single damascene process, vias are etched in apatterned layer of dielectric material and filled with metal toestablish interlevel contacts with a lower conductor. The lowerconductor may be the metallization lines of an underlying level of theinterconnect structure. Trenches are then etched in another patternedlayer of dielectric material and filled with metal to define intralevelmetallization lines. In a dual-damascene process, trenches and vias areetched in a patterned layer of dielectric material and filledsimultaneously by a single blanket deposition of metal. In single anddual-damascene processes, any excess overburden of metal on thedielectric layer is removed from the top of the structure in aplanarization process, such as chemical mechanical polishing (CMP).Silicon oxide and fluorine-doped silicon glass (FSG) are commonmaterials used to form the dielectric layer(s).

Increases in circuit element density as achieved by reducing theline-to-line spacings between adjacent, on-pitch metallization lines ineach interconnect level and between metallization lines in adjacentinterconnect levels. The reduction in line-to-line spacing serves toincrease the line-to-line capacitance, which causes propagation delay byslowing the speed of the signals carried by the metallization lines, andresults in cross talk noise. This increase in line-to-line capacitancemay be offset by reducing the dielectric constant of the dielectricmaterial constituting the dielectric layer(s). Conversely, a reductionin line-to-line capacitance by reducing the dielectric constant permitsconcomitant reductions in line-to-line spacing.

The reduction or elimination of these adverse capacitive couplings couldadvantageously lead to enhanced device speed and reduced powerconsumption. Consequently, a trend in interconnect structures is to formthe dielectric layer from a dielectric material characterized by arelative permittivity or dielectric constant smaller than the dielectricconstant of traditional materials. Candidate low-k materials includeinorganic polymers, organic polymers such as polyamides and SiLK® fromDow Chemical Company, organo-inorganic materials like spin-on glasses,and silsesquioxane-based materials. Generally, these candidate low-kmaterials are characterized by a dielectric constant smaller than three(3).

Damascene processes place stringent requirements on the properties ofthe candidate low-k dielectric materials, which has limited theintegration of low-k dielectrics into damascene processes. Inparticular, a suitable low-k dielectric material must have sufficientmechanical strength and adequate chemical stability to withstand thecleaning, etching, polishing, and thermal treatments imposed bydamascene processing. After manufacture, BEOL interconnect structuresformed using organic dielectric materials have experienced significantreliability problems resulting from mismatches in the thermalcoefficient of expansion with neighboring inorganic materials.

What is needed, therefore, is a low-k dielectric material suitable foruse in forming a structure in an integrated circuit, such as for use asa low-k dielectric layer in a BEOL interconnect structure for anintegrated circuit, that is fully compatible with processes for formingsuch interconnect structures.

SUMMARY OF THE INVENTION

In accordance with an embodiment of the invention, a dielectric materialfor forming a structure of an integrated circuit is comprised of aplurality of carbon nanostructures, such as carbon nanotubes or carbonbuckyballs. In one embodiment of the invention, the nanostructuresforming the dielectric material may be fluorinated. In anotherembodiment of the invention, the dielectric material may have adielectric constant less than about three (3). The dielectric materialmay be used to form a dielectric layer in a semiconductor structure thatincludes at least one conductive feature electrically isolated fromnearby conductive features by portions of the dielectric layer.

In accordance with another embodiment of the invention, a method forforming a dielectric layer includes forming a dielectric layercomprising a plurality of carbon nanostructures on a substrate. Thedielectric layer, which may be applied to the substrate by a spin-onprocess, may be either formed in an insulating electronic state orconverted to the insulating electronic state after formation.

In accordance with another embodiment of the invention, a method forforming a structure for an integrated circuit includes forming adielectric layer including a plurality of carbon nanostructures on asubstrate. The method further includes forming at least one conductivefeature in the dielectric layer.

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BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute apart of this specification, illustrate embodiments of the invention and,together with a general description of the invention given above and thedetailed description of the embodiments given below, serve to explainthe principles of the invention.

FIGS. 1-7 are diagrammatic cross-sectional views of a portion of asubstrate at various stages of a processing method in accordance with anembodiment of the invention;

FIG. 8 is a diagrammatic cross-sectional view similar to FIG. 1 of aportion of a substrate at an initial processing stage in accordance withan alternative embodiment of the invention;

FIG. 9 is a diagrammatic view of a portion of a substrate havingmandrels configured to grow carbon nanotubes to form the dielectriclayer of FIG. 1 in accordance with another alternative embodiment of theinvention; and

FIG. 9A is an enlarged diagrammatic cross-sectional view detailing oneof the mandrels shown in FIG. 9.

DETAILED DESCRIPTION

With reference to FIG. 1, a substrate 10 is covered by a layer 12 of asuitable cap material, such as silicon nitride (Si₃N₄). Substrate 10contains features 11 that are to be contacted, like a silicon diffusionregion (e.g., a source or drain for a semiconductor device) or anunderlying wiring or metallization structure. Substrate 10 may be asemiconductor wafer composed of any semiconductor material including,but not limited to, silicon (Si), silicon germanium (SiGe),silicon-on-insulator, and other like Si-containing semiconductormaterials. The substrate 10 may be doped with either n-type or p-typeimpurities, depending on the desired device or circuit element to befabricated, and may contain various isolation and/or device regionseither formed in the substrate 10 or on a surface thereof. Substrate 10may also be one of the interconnect levels of a multilevel interconnectstructure, a dielectric material, a buried barrier layer, ametallization line, or another substrate that a person of ordinary skillwould recognize as present in integrated circuits.

A layer 14 of a dielectric material overlies the cap layer 12, whichpromotes adhesion between interlevel dielectric 14 and substrate 10. Thedielectric layer 14 is constituted by a network of multiple carbonnanotubes 16 that are individually and collectively characterized by anelectrically-insulating electronic state and, hence, are non-conductingof electrical current. The carbon nanotubes 16 of dielectric layer 14may be applied across substrate 10 in an electrically-insulatingelectronic state or may be converted to an electrically-insulatingelectronic state after layer 14 is formed. The precise arrangement andorientation of the carbon nanotubes 16 is not shown in the FIGS., whichare understood by those of ordinary skill to be diagrammatic. Asnon-limiting examples, the carbon nanotubes 16 may be randomly oriented,substantially parallel and preferentially aligned, or a tangled mat.Generally, carbon nanotubes 16 are hollow cylindrical tubes formed fromprecisely-arranged hexagonal rings of bonded carbon atoms. The carbonnanotubes 16 may, without limitation, be multi-wall nanotubes having astructure resembling nested concentric cylinders or, alternatively, mayconstitute single-wall nanotubes.

In accordance with one embodiment of the invention, dielectric layer 14may be formed by mixing the carbon nanotubes 16 with a solvent-dilutedcopolymer and then depositing the mixture in a liquid form across thesurface of cap layer 12 by a spin-coating process. To that end, amixture of the carbon nanotubes 16, the copolymer, and an appropriatesolvent, such as an alcohol, is dispensed onto cap layer 12 in apredetermined amount and the substrate 10 is rapidly rotated or spun.The spin-on process uniformly distributes the liquid across the caplayer 12 by centrifugal forces and results in a uniform applied film ofa controlled thickness. The liquid film is solidified by alow-temperature hot plate bake that removes residual solvent and curesthe copolymer. Typically, the hot plate bake is performed at atemperature of from about 90° C. to about 400° C. for a time periodranging from about 10 seconds to about 300 seconds. The residualcopolymer operates as a binder for the carbon nanotubes 16 after thesolvent is removed. Suitable spin on organic copolymers include SiLK®sold by Dow Chemical Company, the fluorinated aromatic resin FLARE® soldby Honeywell Electronic Materials, perfluorocyclobutane (PFCB) aromaticether polymers commercially available from Dow Chemical Company, each ofwhich has a dielectric constant less than about three (3), and otherhigh temperature stable materials such as polyimides. Even if thecontribution of the binding copolymer to the effective dielectricconstant of dielectric layer 14 is taken into consideration, dielectriclayer 14 has a dielectric constant of less than about three (3) when thecarbon nanotubes 16 are in the electrically-insulating electronic state,as described below.

In an alternative embodiment of the invention, the dielectric layer 14may be formed from electrically-insulating C₆₀ or C₇₀ buckyballs ormulti-wall buckyballs, instead of carbon nanotubes 16 or in a mixturewith carbon nanotubes 16, that are deposited by spin coating, asdescribed above. Buckyballs typically have a shape resembling a soccerball with a lattice formed primarily from six-fold rings (hexagonalstructure), with occasional five-fold rings and seven-fold rings.Buckyballs may be formed by a conventional process, such as thoseprocesses disclosed in U.S. Pat. No. 5,227,038 (Smalley et al.) and U.S.Pat. No. 5,300,203 (Smalley), each of which is hereby incorporated byreference herein in its entirety. The buckyballs are converted to theinsulating electronic state by, for example, fluorination, as describedherein, so that the buckyballs are non-conducting electrically. Theinvention contemplates that other types of carbon-based nanostructuressimilar to carbon nanotubes 16 and carbon buckyballs may be used forforming the dielectric layer 14.

The carbon nanotubes 16 may be converted from their as-appliedelectronic state to an electrically-insulating electronic state afterdielectric layer 14 is formed. In one embodiment of the invention, theconversion to an electrically-insulating electronic state may occurimmediately after the dielectric layer 14 is formed. In anotherembodiment of the invention, the conversion may occur during asubsequent processing stage. Alternatively, the carbon nanotubes 16 maybe converted to the electrically-insulating state before the dielectriclayer 14 is formed by the spin-on process. The carbon nanotubes 16 mayalso be grown on substrate 10 in either a semiconducting or conductingelectronic state, as described below with regard to FIGS. 8 and 9, andconverted to an insulating electronic state. Regardless of the formationtechnique, the resultant dielectric layer 14 constructed from carbonnanotubes 16 will have a dielectric constant of less than about three(3) when the carbon nanotubes 16 are in the electrically-insulatingelectronic state.

One approach for converting the carbon nanotubes 16 from asemiconducting or conducting electronic state to anelectrically-insulating electronic state involves fluorination. Anexemplary conversion process involves exposing the carbon nanotubes 16to a fluorine-containing atmosphere (e.g., fluorine gas (F₂)) at anelevated temperature (e.g., 50° C. to 250° C.) and for a durationsufficient to provide a suitable degree of fluorination. Thefluorine-containing atmosphere may be diluted with a gaseous diluentincluding, but not limited to, nitrogen (N₂) and inert gases, such asargon (Ar). Treatment of carbon nanotubes by fluorination at elevatedtemperatures is disclosed, for example, in Mickelson et al., Chem. Phys.Lett. 296 (1998) pp. 188-194, Bahr et al., J. Mater. Chem. 12 (2002) pp.1952-1958, Mickelson et al., J. Phys. Chem. B (1999) pp. 4318-4312, Boulet al., Chem. Phys. Lett. 310 (1999) 367-372, and U.S. Pat. No.6,645,455 (Margrave et al.), each of which is hereby incorporated byreference herein in its entirety. The fluorine-containing gas willpermeate the dielectric layer 14 and react with the carbon nanotubes 16at the elevated temperature to provide the electrically-insulatingelectronic state. The carbon nanotubes 16 may be fluorinated beforebeing applied by the spin-coating process, immediately after thedielectric layer 14 is formed, or during a subsequent process stage.Alternatively, the carbon nanotubes 16 may be hydrogenated or alkylatedto convert to an insulating electronic state.

With reference to FIG. 2 in which like reference numerals refer to likefeatures in FIG. 1 and at a subsequent fabrication stage, a cap layer 18is deposited on the dielectric layer 14. The cap layer 18 operates toseal the upper horizontal surface of the dielectric layer 14 by fillingthe open spaces or gaps between adjacent carbon nanotubes 16. The caplayer 18 may have an upper boundary that is coplanar with the horizontalupper surface of the dielectric layer 14, as shown in FIG. 2.Alternatively, cap layer 18 may project partially above the horizontalupper surface of dielectric layer 14 or may reside entirely on top ofthe dielectric layer 14. The tips or free ends of some of the carbonnanotubes 16, of which carbon nanotubes 19 are representative, mayproject above the horizontal upper surface of cap layer 18. Theseprojecting nanotubes 19 are preferably removed by a planarizationtechnique, such as a chemical-mechanical polishing (CMP) process, sothat the upper horizontal surface of cap layer 18 is polished flat andplanarized. Any residual metal catalyst exposed by polishing cap layer18 may be oxidized with an aqueous peroxide wash or with a brief oxygenplasma treatment. This oxidizing step applies to those embodiments ofthe invention described in FIGS. 8 and 9 in which the dielectric layer14 is grown using a catalyst.

With reference to FIG. 3 in which like reference numerals refer to likefeatures in FIG. 2 and at a subsequent fabrication stage, openings 20characteristic of a pattern of vias and trenches are formed in cap layer18 and the dielectric layer 14. The openings 20 are defined usingconventional lithography, including applying a photoresist to a surfaceof the cap layer 18 and patterning the photoresist, and then etchingusing the patterned photoresist. Suitable etching processes include anyconventional dry etching process, such as reactive-ion etching andplasma etching. The etching process stops vertically on the cap layer12. However, the invention does not require that all of the openings 20formed across the substrate 10 extend to the depth of the cap layer 12.

The openings 20 of the pattern may include, for example, an interconnectstructure of features, such as vias and trenches, that are filled with aconductive material and thereby coupled with underlying conductivefeatures (not shown), such as metallization lines or underlying circuitelements previously formed in the substrate 10. The interconnectstructure may be, for example, a damascene structure or a doubledamascene structure but the invention is not so limited. The pattern caninclude any desired pattern of trenches, vias and other featuresconventionally designed into such interconnect structures as demanded bydesign requirements.

If the carbon nanotubes 16 have not been previously converted to aninsulating electronic state, the openings 20 afford access forperforming the conversion at this stage of the fabrication process. Morespecifically, fluorination gas vertically accesses the full thickness ofthe dielectric layer 14 through the openings 20 and diffuses laterallythrough the dielectric layer 14.

With reference to FIG. 4 in which like reference numerals refer to likefeatures in FIG. 3 and at a subsequent fabrication stage, the carbonnanotubes 16 of dielectric layer 14 bordering the vertical sidewalls ofopenings 20 are sealed with a layer 22 of a diffusion limiteddielectric, like Si₃N₄ or silicon dioxide (SiO₂). Dielectric layer 22prevents migration of metal from the subsequent contacts formed inopenings 20 into the dielectric layer 14. The dielectric layer 22 may beformed, for example, by a chemical vapor deposition (CVD) process. Thedielectric layer 22 may have a vertical boundary that is substantiallycoplanar with the vertical sidewalls of openings 20, as shown in FIG. 4.Alternatively, dielectric layer 22 may partially or totally cover thevertical sidewalls of openings 20. A directional dry etch process, suchas RIE, is used to remove portions (not shown) of the dielectric layer22 from the horizontal floor of each opening 20.

With reference to FIG. 5 in which like reference numerals refer to likefeatures in FIG. 4 and at a subsequent fabrication stage, an optionalbut preferred liner 24 is applied to the exposed vertical and horizontalsurfaces of the openings 20. Liner 24 is typically comprised of one ormore layers of tantalum (Ta), titanium (Ti), tungsten (W), or nitridesof these metals. The liner material of liner 24 may be formed in theopenings 20 utilizing conventional deposition processes well known topersons of ordinary skill in the art, including but not limited to CVD,plasma-enhanced CVD, and physical vapor deposition (PVD). The processapplying the liner 24 inside openings 20 may also cover cap layer 18with excess liner material that is subsequently removed.

With reference to FIG. 6 in which like reference numerals refer to likefeatures in FIG. 5 and at a subsequent fabrication stage, a layer of aconductor 26 is deposited across the substrate 10 so that the openings20 (FIG. 3) are filled by conductive material. The conductive materialmay be a metal that will serve as contacts with the metal conductivelines of underlying circuit elements or devices previously formed in thesubstrate 10 and as metal conductive lines. The optional liner 24, alongwith the dielectric layer 22, separate the dielectric layer 14 fromportions of the conductor layer 26 filling openings 20. Suitableconductors include but are not limited to aluminum (Al), copper (Cu),tungsten (W), silver (Ag), alloys of these metals, and other likemetals. The metal is formed in the openings 20 utilizing a conventionaldeposition process such as CVD, plasma-enhanced CVD, an electrochemicalprocess such as electroplating or electroless plating, PVD, directcurrent (DC) or radio frequency (RF) sputtering, and the like.

With reference to FIG. 7 in which like reference numerals refer to likefeatures in FIG. 6 and at a subsequent fabrication stage, the topsurface of conductor layer 26 is made substantially coplanar with theupper horizontal surface of cap layer 18, usually by a CMP process, todefine individual conductive features or contacts 28 inside openings 20.The CMP process combines abrasion and dissolution to flatten andsmoothen the surface relief. Abrasion occurs when higher portions of theconductive layer 26 contact a polish pad and abrasive particles in apolish slurry and become subject to mechanical forces. Dissolutionoccurs when conductive material at the exposed surface of layer 26contacts chemicals in the slurry and becomes susceptible to chemical orelectrochemical reactions. The planarization removes the overburden ofexcess conductive material from layer 26 and portions of the optionalliner 24 covering the cap layer 12 outside of openings 20 (FIG. 4).

The cap layer 18 remains on the surface of the interconnect structureafter planarization. For this reason, the dielectric constant of the caplayer 18 should be relatively low so as to not significantly increasethe effective dielectric constant of the dielectric layer 14.Accordingly, the dielectric layer 14 and the cap layer 18 shouldcollectively have a dielectric constant of less than about three (3).However, in certain embodiments, the dielectric layer 14 alone has adielectric constant of about three (3) with the presence of the caplayer 18 resulting in an effective dielectric constant marginallygreater than about three (3). After planarization, an upper horizontalsurface of each conductive contact 28 is approximately flat and levelwith the upper horizontal surface of cap layer 12 across the substrate10.

The completed interconnect structure of FIG. 7 is reproduced orreplicated across the surface of substrate 10 by the fabricationprocedure described in FIGS. 1-7 to define an interconnect level.Additional interconnect levels, similar or identical to the completedinterconnect level, may be stacked above the completed interconnectlevel by following a fabrication process identical or similar to thatillustrated in FIGS. 1-7. The invention contemplates that accesspassages (not shown) may be provided in such multilevel interconnectstructures for converting the constituent carbon nanotubes 16 to aninsulating electronic state after all levels are formed. For example, afluorination gas may be routed to the dielectric layer 14 of the variouslevels through the access passages. Regardless of the processing stageat which the conversion of carbon nanotubes 16 to an insulatingelectronic state occurs, the temperature of the substrate 10 afterconversion and during subsequent processing stages should not exceed atemperature that would otherwise degrade the electrical insulatingproperties of the converted carbon nanotubes 16.

The spin-coating process offers benefits of a low-temperature processand simplicity. However, the carbon nanotubes 16 of dielectric layer 14may be formed by other techniques. For example, the carbon nanotubes 16may be grown using any suitable growth technique, as described below.

With reference to FIG. 8 in which like reference numerals refer to likefeatures in FIG. 1 and in accordance with an alterative embodiment ofthe invention, the carbon nanotubes 16 may be grown by a CVD process ora plasma-enhanced CVD process. To that end, a thin layer 30 of acatalyst is formed on the cap layer 12. The catalyst layer 30 mayinclude any material capable of nucleating and supporting the synthesisor growth of carbon nanotubes 16 when exposed to appropriate reactantsunder chemical reaction conditions suitable to promote nanotube growth.Suitable catalyst materials for catalyst layer 30 include, but are notlimited to, iron (Fe), nickel (Ni), cobalt (Co), compounds of thesemetals such as metal oxides, and alloys of these metals. In the case ofmetal oxides, it may be necessary to perform a reduction to access oractivate the catalyst material. The catalyst layer 30 is formed bydepositing the catalytic material by any conventional depositiontechnique including, but not limited to, a CVD process orplasma-enhanced CVD process, DC or RF sputtering, and PVD.

The catalyst layer 30 catalyzes the growth of carbon nanotubes 16 from acarbon-containing reactant gas when contacted by the reactant gas underappropriate growth conditions. Suitable carbon-containing reactant gasesfor such catalyzed nanotube growth include, but are not limited to,carbon monoxide and hydrocarbon precursors. The hydrocarbon precursormay be an aromatic hydrocarbon, such as benzene, toluene, xylene,cumene, ethylbenzene, naphthalene, phenanthrene, anthracene, and theirmixtures. Alternatively, the hydrocarbon precursor may be a non-aromatichydrocarbon, such as methane, ethane, propane, ethylene, propylene,acetylene, and their mixtures, or an oxygen-containing hydrocarbon, suchas methanol, ethanol and other alcohols, acetone and other ketones,formaldehyde, acetaldehyde and other aldehydes, and their mixtures.Other suitable reactant gases include a mixture of carbon monoxide andhydrogen, a mixture of acetylene and ammonia, a mixture of acetylene andhydrogen, and a mixture of ethanol and nitrogen.

The catalyst layer 30 promotes carbon nanotube synthesis by reducing theactivation energy of the reaction with the carbon-containing reactantgas forming carbon nanotubes 16. Carbon atoms originating from thereactant gas are incorporated into the lengthening carbon nanotubes 16.Substrate 10 may be heated to a temperature adequate to promote and/orhasten CVD growth. The carbon nanotubes 16 will tend to grow verticallyfrom the catalyst layer 30. Growth is halted when the carbon nanotubes16 have a desired height. The carbon nanotubes 16 grow on substrate 10in either a semiconducting or conducting electronic state and areconverted to an insulating electronic state by, for example,fluorination or hydrogenation as described herein. Conversion of thecarbon nanotubes 16 by fluorination would also fluorinate the remainingportions of catalyst layer 30 to produce a metal fluoride.

After the carbon nanotubes 16 are grown, processing of substrate 10continues as described herein with regard to FIGS. 1-7 to form thecompleted interconnect structure shown in FIG. 7. Of course, it isunderstood by person of ordinary skill that, after the carbon nanotubes16 are formed, the catalyst layer 30 is converted to a nonconductiveform by, for example, oxidation or fluorination.

With reference to FIGS. 9 and 9A in which like reference numerals referto like features in FIG. 1 and in accordance with an alterativeembodiment of the invention, the dielectric layer 14 may be formed byanother approach. Specifically, a thin layer 31 of a material that doesnot support the growth of carbon nanotubes 16 is deposited acrosssubstrate 10 on the cap layer 12 and an oxide layer having a thicknessin the range of about 200 nm to about 800 nm is formed on layer 31.Then, a thin layer 34 of a material that does not support the growth ofcarbon nanotubes 16 is deposited on the oxide layer. Layers 31 and 34may be formed from materials such as silicon, tungsten, titanium,zirconium, hafnium, and aluminum, and may have a thickness in the rangeof about 10 nm to about 20 nm.

A plurality of parallel mandrels 32 are formed from the oxide layer onthe metal layer 31 using a conventional lithography and etch processthat removes patterned portions of the oxide layer and layer 34.Adjacent parallel mandrels 32 in the pattern may be separated, forexample, by about 300 microns to about 1000 microns. After etching, anupper horizontal surface of an oxide body 36 of each mandrel 32 iscovered by a residual cap that represents residual material left afteretching layer 34 and the vertical sidewalls of the oxide body 36 areexposed oxide. This structure is best shown in FIG. 9A. The remainingmaterial of layers 31 and 34 may be rendered non-conducting, after thecarbon nanotubes 16 are grown, by either fluorinating simultaneouslywith the fluorination of the carbon nanotubes 16 or oxidizing witheither oxygen or ozone at a low temperature that does not causesignificant oxidation of the carbon nanotubes 16.

Carbon nanotube growth is initiated by a CVD process that supplies aflow of a gas mixture of a catalyst vapor or gas, such as ferrocene(Fe(C₅H₅)₂), and a carbon-containing vapor of gas, such as xylene(C₆H₄(CH₃)₂), that is directed approximately horizontally across thesurface of substrate 10, as generally indicated by the arrows labeledwith reference numeral 38. The layers 31 and 34 do not support carbonnanotube growth. However, the reactant gas reacts with the catalystatoms deposited from the catalyst gas on the exposed vertical sidewallsof the oxide body 36 to nucleate and grow carbon nanotubes 16. Thepresence of the catalyst gas in the gas mixture permits nucleation andgrowth of carbon nanotubes 16 without incorporating a metal nucleatinglayer 30 (FIG. 8) into the interconnect structure. During the chemicalvapor decomposition, metal atoms from the catalyst gas in the gasmixture serve to nucleate the nanotubes 16 on the vertical sidewalls ofthe oxide body 36.

Carbon nanotubes 16 grow outwardly from the sidewalls with asubstantially horizontal orientation that extends approximatelylaterally across the substrate surface, as shown in dashed lines in FIG.9A. The CVD process is sustained to continue nanotube growth until thelength of carbon nanotubes 16 is suitable for forming the dielectriclayer 14. The carbon nanotubes 16 grow on substrate 10 in either asemiconducting or conducting electronic state and are converted to aninsulating electronic state by, for example, fluorination orhydrogenation as described herein. A dielectric layer 14 formed withcarbon nanotubes 16 grown in this manner may solve the problem ofthermal expansion of conventional organic materials as dielectric layer14 is not constrained vertically, which permits expansion without theintroduction of stress.

After the carbon nanotubes 16 are grown, processing of substrate 10continues as described herein with regard to FIGS. 1-7 to form thecompleted interconnect structure shown in FIG. 7. Of course, it isunderstood by person of ordinary skill that the metal capped mandrels 32will be present in the completed interconnect structure or may beremoved, if desired, from the completed interconnect structure by a dryetch process like RIE.

References herein to terms such as “vertical”, “horizontal”, etc. aremade by way of example, and not by way of limitation, to establish aframe of reference. The term “horizontal” as used herein is defined as aplane parallel to the conventional plane or surface of substrate 10,regardless of orientation. The term “vertical” refers to a directionperpendicular to the horizontal, as just defined. Terms, such as “on”,“above”, “below”, “side” (as in “sidewall”), “higher”, “lower”, “over”,“beneath” and “under”, are defined with respect to the horizontal plane.It is understood that various other frames of reference may be employedwithout departing from the spirit and scope of the invention.

The fabrication of the semiconductor device has been described by aspecific order of fabrication stages and steps. However, it isunderstood that the order may differ from that described. For example,the order of two or more steps may be altered relative to the ordershown. Also, two or more steps may be carried out concurrently or withpartial concurrence. In addition, various steps may be omitted and othersteps may be added. It is understood that all such variations are withinthe scope of the invention.

While the present invention has been illustrated by a description ofvarious embodiments and while these embodiments have been described inconsiderable detail, it is not the intention of the applicants torestrict or in any way limit the scope of the appended claims to suchdetail. Additional advantages and modifications will readily appear tothose skilled in the art. Thus, the invention in its broader aspects istherefore not limited to the specific details, representative apparatusand method, and illustrative example shown and described. Accordingly,departures may be made from such details without departing from thespirit or scope of applicants' general inventive concept.

1. An integrated circuit structure formed on a substrate, comprising: afirst dielectric layer comprising a plurality of fluorinated carbonnanostructures and a copolymer layer binding said fluorinated carbonnanostructures; an opening with a sidewall extending into said firstdielectric layer; a conductive feature disposed in said opening in saidfirst dielectric layer, said conductive feature electrically isolatedfrom nearby conductive features by portions of said first dielectriclayer; and a second dielectric layer disposed in said opening betweensaid conductive feature and said first dielectric layer, said seconddielectric layer comprising a dielectric material that preventsmigration of conductive material from said conductive feature throughsaid sidewall and into said first dielectric layer.
 2. The integratedcircuit structure of claim 1 wherein said first dielectric layer has anexposed surface, and further comprising: a cap layer at least partiallycovering said exposed surface, said cap layer having a top surface, andsaid conductive feature having a top surface substantially coplanar withsaid top surface of said cap layer.
 3. The integrated circuit structureof claim 1 wherein said fluorinated carbon nanostructures comprise aplurality of fluorinated carbon nanotubes.
 4. The integrated circuitstructure of claim 1 wherein said first dielectric layer has adielectric constant of less than about
 3. 5. The integrated circuitstructure of claim 1 wherein said structure comprises a plurality ofconductive features electrically isolated by portions of said dielectriclayer.
 6. The integrated circuit structure of claim 1 wherein saidfluorinated carbon nanostructures comprise a plurality of fluorinatedcarbon buckyballs.
 7. The integrated circuit structure of claim 1further comprising: a cap layer disposed on said first dielectric layer.8. The integrated circuit structure of claim 7 wherein said fluorinatedcarbon nanostructures, said copolymer layer, and said cap layercollectively have a dielectric constant of less than about
 3. 9. Theintegrated circuit structure of claim 1 further comprising: a substrateselected from the group consisting of an interconnect level, adielectric material, a buried barrier layer, a metallization line, and asemiconductor wafer.
 10. An integrated circuit comprising a plurality ofcircuit elements and the integrated circuit structure of claim 1, saidconductive feature being electrically coupled with at least one of saidcircuit elements.
 11. The integrated circuit structure of claim 1wherein said fluorinated carbon nanostructures and said copolymer layerhave an effective dielectric constant of less than about
 3. 12. Theintegrated circuit structure of claim 1 further comprising: a pluralityof mandrels in said first dielectric layer, each of said mandrelsincluding sidewalls from which said fluorinated carbon nanostructuresproject into said copolymer layer.
 13. The integrated circuit structureof claim 1 further comprising: a catalyst layer bordering said firstdielectric layer, said catalyst layer comprising a metal-containingmaterial capable of promoting synthesis of said fluorinated carbonnanostructures.
 14. The integrated circuit structure of claim 1 furthercomprising: a liner layer of a conductive material disposed between saidsecond dielectric layer and said conductive feature.